The present invention relates generally to transistor logic circuits and more specifically to transistor logic circuits used for high speed transistor logic.
Several different logic design technologies are used in implementing circuits, where the particular logic design technology used depends on factors such as speed, power and voltage constraints. One such logic design technology is HSTL (High Speed Transistor Logic). With HSTL, a logical high output (xe2x80x9c1xe2x80x9d or VOH) is represented by a voltage of about 1.5 volts, while a logical low output (xe2x80x9c0xe2x80x9d or VOL) is represented by a voltage of about 0.8 volts. In addition, the characteristic impedance, Z0, of an HSTL output is usually 50 ohms terminated to 1.5 volts. The rise and fall times for transitions between logical levels are specified to be around 200 to 300 picoseconds (ps).
FIG. 1 shows a typical output driver that might be used to provide an HSTL signal output. The output driver is shown comprising transistors Q1, Q2, Q3, Q4, a current source I1, a termination resistor RT and a bias resistor R3. In operation, Q1 and Q2 form a current mirror, with the current source I1 providing current to Q1 and a pull-up circuit (Q4, RT) providing current to Q2. Q3 and R3 are provided to correct for beta error in the current mirror.
One problem with the output driver shown in FIG. 1 is that, if R3 is large, it will prevent a quick turn off of Q2 at the beginning of a rising edge of the output. This occurs because, as drive transistor Q2 is turning off, current from the output leaks to the base of drive transistor Q2 through the base-collector parasitic capacitance of Q2. If R3 is small, that parasitic current flows through R3, but when R3 is large, that parasitic current ends up being additional base current through Q2, thus preventing a quick turn off of Q2.
FIG. 2 is a schematic illustrating one solution that has been used to address the above problem. As shown in the schematic, a control transistor Q5 is coupled between the base of a drive transistor Q2 and ground. The base voltage of control transistor Q5 is set by a resistor R6, inserted between the base of Q2 and the base of Q5, and by a Shottky diode reverse biased between the base of Q5 and ground. Another Shottky diode D3 is provided between the output and the base of Q5, to act as a capacitor to turn on Q5 when the output voltage rises. Alternatively, D3 could be replaced with a capacitor.
In the circuit shown in FIG. 2, D2 creates a recovery path or clamping action at the base of Q5. By the action of D3 (or a capacitor used in its place), the base of Q5 rises as voltage at the output rises. This capacitive coupling causes Q5 to turn on when the output rises, thus helping Q2 to turn off. That same capacitive coupling causes the base of Q5 to go negative when the output voltage falls. Without D2, the base of Q5 would go negative enough to reach xe2x88x92VOH+VOLxe2x88x92VBE, or roughly xe2x88x923 volts. If the base of Q5 did get that negative, a recovery period would be required to recharge the base of Q5, normally through current passed through R6. However, with D2 present, the lower voltage at the base of Q5 is clamped at xe2x88x92VSBD (about xe2x88x920.5 volts), so the base of Q5 recovers faster.
While the circuit shown in FIG. 2 may shorten the rise time of the output, it is subject to a number of process variations that might be difficult to control, such as the resistance of R6, the capacitance of D3 and the turn-on voltage of Q5.
The present invention provides an improved output driver for HSTL. In one embodiment of an output driver according to the present invention, a bias control transistor is provided to absorb current leaking through the base-collector capacitance of the drive transistor and maintain the base voltage on the drive transistor. The bias control transistor is biased by a series network that urges the bias control transistor to a bias near the bias control transistor""s turn-on bias, with a feedback capacitor coupled between the output and the base of the bias control transistor to turn on the bias control transistor when the output rises.
One advantage of the present invention is that it provides a circuit that creates a transient pull-down current for a high speed transistor logic family with controlled characteristic impedance and low level output voltages.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.